This disclosure relates generally to semiconductor devices and more specifically to a two-step silicide formation process to reduce parasitic source/drain resistance and parasitic gate-to-source/drain capacitance.
A typical semiconductor transistor device comprises a gate, which has a conductive element stacked onto a dielectric layer on a semiconductor substrate, and doped regions within the substrate on either side of the gate. The dielectric layer is typically an oxide and is often referred to as the gate oxide. One doped region is referred to as a source, the other as a drain, indicating the direction of current flow. Other than where current is applied, these doped regions are similar in all other respects, and hence a doped region may be referred to as a source/drain region, as it could be either the source or the drain depending on implementation. Also common in semiconductor devices, adjoining a source/drain region, is another similarly doped region extending the source/drain region towards the gate. This other region is commonly referred to as the extension region and is shallower than the source/drain region.
As the size of integrated circuits (ICs) decrease, parasitic resistance and capacitance may be increased due to the smaller sizes and closer proximity of contacts within a semiconductor device. A contact is the electrical connection between an active region within the device, e.g., a source/drain region or gate, and a metal layer. Silicide (metal-silicon compounds) contacts have become increasingly important to reduce electrical resistance. By increasing contact of a silicide layer with a source/drain region, resistance may be lowered further. However, in semiconductor devices with conventional silicides, the closer such contacts get to a gate, the higher the likelihood of increased parasitic gate-to-source, or gate-to-drain, capacitance. The reason has to do with junction leakage. As the silicide is pushed closer to the gate, it is also pushed closer to the source/body and drain/body junctions, resulting in higher trap-assisted junction leakage due to metal diffusion from a silicide that has finite thermal stability. To keep junction leakage low, the silicide-to-junction proximity must not fall below some threshold value, which means that moving a conventional silicide closer to the gate requires making the source/drain junctions deeper both laterally and vertically. Therefore, the gate-to-source/drain capacitance increases and the placement, type, and structure of silicide layer(s) may become a compromise between parasitic source/drain resistance and parasitic gate-to-source/drain capacitance.